FPGAでのLチカをVerilog HDLで理解する（ソースコード）

連載「MAX 10 FPGAで学ぶFPGA開発入門」の第3回、「FPGAでのLチカをVerilog HDLで理解する」のソースコードです。

[PR／MONOist]

PR

・FPGAでのLチカをVerilog HDLで理解する

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Axelsys
// Engineer: Greg Miller
// 
// Create Date:    11:21:08 08/21/2014 
// Design Name:    LED
// Module Name:    LED_Verilog 
// Project Name:   Altera MAX10 Breakout Board
// Target Devices: 10M08SAE144C7G
// Tool versions: 14.0
// Description: 
// LEDs, D1 through D5 will blink on for 1/2 second and off for 1/2 second.
// Clock is operating at 50MHz.
// 
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module LED_Flash_all(
    input clk,
    output LED1,
    output LED2,
    output LED3,
    output LED4,
    output LED5
    );
 
	reg[15:0] div_cntr1;
	reg[9:0] div_cntr2;
	reg dec_cntr;
	reg half_sec_pulse;
	
	initial begin
		div_cntr1 = 0;
		div_cntr2 = 0;
		dec_cntr  = 0;
		end
		
	
	always@(posedge clk)
		begin
		div_cntr1 <= div_cntr1 + 1;
		if (div_cntr1 == 0) 
			if (div_cntr2 == 762) 
				begin
				div_cntr2 <= 0;
				half_sec_pulse <= 1;  
				end
			else
				div_cntr2 <= div_cntr2 + 1;
		else
			half_sec_pulse <= 0;
		
		if (half_sec_pulse == 1)	
			dec_cntr <= !dec_cntr;
			
		end	
		
		
	assign LED1 = dec_cntr ;
	assign LED2 = dec_cntr ;
	assign LED3 = dec_cntr ;
	assign LED4 = dec_cntr;
	assign LED5 = dec_cntr ;
				
endmodule

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