module dff_test; reg CLK, D; wire X, Y, Z; dff i0(CLK, D, X, Y, Z); always #5 CLK = ~CLK; initial begin CLK = 0; D = 0; #30 D = 1; #50 D = 0; #30 D = 1; #50 D = 0; #30 $finish; end initial begin $monitor("CLK=%d, D=%d, X=%d, Y=%d, Z=%d", CLK, D, X, Y, Z); $dumpfile("dump.vcd"); $dumpvars(0, dff_test); end endmodule