module UPDOWN(RESET, CLK, DEC, COUNT, CARRY); input RESET, CLK, DEC; output [3:0] COUNT; output CARRY; parameter SEC1_MAX = 6000000; // 6MHz reg [22:0] tmp_count; reg [3:0] COUNT_TMP; wire ENABLE; reg CARRY; always @(posedge CLK or negedge RESET) begin if (RESET == 1'b0) tmp_count <= 23'h000000; // else else if (ENABLE == 1'b1) tmp_count <= 23'h000000; else tmp_count <= tmp_count + 23'h1; end // assign DIVIDE_CLK = tmp_count[22]; assign ENABLE = (tmp_count == (SEC1_MAX - 1))? 1'b1 : 1'b0; //always @(posedge DIVIDE_CLK or negedge RESET) always @(posedge CLK or negedge RESET) begin if (RESET == 1'b0) begin COUNT_TMP <= 4'h0; CARRY <= 1'b0; end else if (ENABLE == 1'b1) // else if (DEC == 1'b1) if (DEC == 1'b1) if (COUNT_TMP == 4'h9) begin COUNT_TMP <= 4'h0; CARRY <= 1'b1; end else begin COUNT_TMP <= COUNT_TMP + 4'h1; CARRY <= 1'b0; end else if (COUNT_TMP == 4'h0) begin COUNT_TMP <= 4'h9; CARRY <= 1'b1; end else begin COUNT_TMP <= COUNT_TMP - 4'h1; CARRY <= 1'b0; end end assign COUNT = COUNT_TMP; endmodule